ELK 453E — Industrial Applications of Power Electronics  ·  İTÜ

500 W, 400 V, 50 kHz
Single-Phase Boost PFC Converter

Design, Component Sizing, Control and Model-Based Verification (MIL / SIL / PIL)

Authors: Enes Aytuğ Kır (040240785) & Ufuk Barın (040240791) Coordinator: Prof. Dr. S. Barış Öztürk Institution: Istanbul Technical University (İTÜ)
0.99
Power Factor
4.48%
Current THD
400 V
Vout
500 W
Rated Power
50 kHz
fsw
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Background

What is PFC and Why Do We Need It?

  • A standard diode bridge with a bulk capacitor draws current only near the voltage peaks — the line current is spiky and non-sinusoidal.
  • This lowers the power factor and injects significant current harmonics into the grid, wasting distribution capacity.
  • A boost PFC stage forces the input current to be sinusoidal and in phase with the voltage, driving the power factor toward unity.
  • Key benefits: compliance with harmonic standards (e.g. IEC 61000-3-2), lower RMS current, and better utilisation of the supply.
  • Real-world applications: server & PC power supplies, LED drivers, EV chargers, appliance motor drives.

Design Specifications (Table 1)

\(V_{\text{in (RMS)}}\)\(240 \text{ V}_{\text{rms}}\)
\(f_{\text{line}}\)50 Hz
\(V_o\)400 V
\(P_o\)500 W
\(f_s\)50 kHz
Δ\(V_o\)/\(V_o\)< 1%
\(\hat{V}_p \text{ (carrier)}\)3 V
Architecture

Converter Topology & Control Structure

  • Power path: AC mains → EMI filter → full-wave diode-bridge rectifier producing \(v_{\text{rect}}(t) = V_{\text{in,pk}}|\sin(\omega t)|\).
  • Boost stage: inductor L, MOSFET S, ultrafast diode D, bulk output capacitor \(C_o\) feeding load R = \(V_o\)²/\(P_o\).
  • Dual-loop cascaded average current-mode control: a fast inner current loop (Gci) nested inside a slow outer voltage loop (Gcv).
  • A multiplier/divider builds the sinusoidal current reference: \(i_{\text{ref}} = \frac{v_{\text{ea}} \cdot v_{\text{rect}}}{V_{\text{rms}}^2}\).
  • PWM modulator uses a 3 V sawtooth carrier at 50 kHz. Control scheme follows TI Application Report SPRA902A.
Converter block diagram and control structure
Design Maths

Mathematical Component Sizing

  • Operating point: \(V_{\text{in,pk}}\) = √2 × 240 = 339.41 V; \(I_{\text{in}} = \frac{500}{240} = \mathbf{2.083 \text{ A}_{\text{rms}}}\); \(I_{\text{in,pk}}\) = 2.946 A; \(I_o = \mathbf{1.25 \text{ A}}\); \(R = \mathbf{320 \ \Omega}\).
  • Duty cycle range: d = 1 − \(V_{\text{in,pk}}\)·|sin|/\(V_o\) → \(d_{\text{min}}\) = 0.1515 at the line peak; clamped to d ≤ 0.95 near zero-crossings.
  • Boost inductor: CCM ripple rule with k = 0.4 gives L ≥ 0.872 mH. Chosen L = 12 mH for low ripple (\(\Delta i_{L,\text{pk}}\) ≈ 0.0857 A, ~2.9% of \(I_{\text{in,pk}}\)) and robust CCM.
  • Output capacitor: 2nd-harmonic ripple equation with 1% limit requires \(C_o\) ≥ 994.7 µF. Chosen \(C_o\) = 1500 µF → \(\Delta V_{o,\text{pp}}\) = 2.65 V → 0.66% < 1%.
  • Semiconductors: MOSFET 600 V / 10 A (\(I_{S,\text{pk}}\) = 3.29 A); boost diode 600 V / 5 A; diode bridge 600 V / 6 A.
  • Every value traces back to a closed-form equation in the report — not a trial number.

Chosen Passive Values

Inductor L12 mH
Capacitor \(C_o\)1500 µF
\(\Delta V_{o,\text{pp}}\)2.65 V (0.66%)
\(\Delta i_{L,\text{pk}}\)0.0857 A
MOSFET600 V / 10 A
Boost Diode600 V / 5 A
Modelling

Average Model of the Converter

  • Switched state equations written for MOSFET-on and MOSFET-off subintervals.
  • A moving-average operator over one switching period removes switching-frequency ripple, leaving only the envelope.
  • Result: a bilinear large-signal averaged state-space model (duty ratio multiplies the states).
  • Quasi steady-state argument recovers: \(\langle v_o \rangle = \frac{\langle v_{\text{rect}} \rangle}{1-d}\) and ⟨iL⟩ = \(I_{\text{in,pk}}\)·|sin(ωt)|.
  • Open-loop simulation confirms the power stage sits in the correct operating region (\(V_o\) ≈ 400 V).
Open-loop average model — DC-side output voltage Vout and inductor current IL
Open-loop average model — input side vin and iin
Small-Signal Analysis

Small-Signal Plants & Bode Analysis

  • Linearised around the rated operating point.
  • Current plant \(G_{id}(s)\) = \(V_o\)(1 + sR\(C_o\)) / (s²L\(C_o\)R + sL + R) — duty → inductor current. LC resonance ≈ 37.5 Hz. At target crossover 5 kHz: |Gid| = 0.515 dB, phase ≈ −90°.
  • Voltage plant \(G_{vi}(s)\) = R/(1 + sR\(C_o\)) — inductor current → output voltage. Output pole ≈ 0.332 Hz. At target crossover 2.5 Hz: |Gvi| = 32.48 dB, phase ≈ −82.45°.
  • Both plants confirm the need for separate bandwidth targets: the current loop must be fast (kHz range) while the voltage loop must be slow (sub-10 Hz) to avoid distorting the sinusoidal reference.
Bode plots of the current plant \(G_{id}(s)\) and voltage plant \(G_{vi}(s)\)
Controller Design

PI Controller Design & Re-Tuning

  • Started from textbook PI gains aimed at the 5 kHz / 2.5 Hz crossover targets.
  • Those gains kept input-current THD stuck above the 5% limit, regardless of gain adjustments.
  • Several PI gain sets were evaluated through simulation. The final gains were selected based on the best combined THD, PF, and output-voltage regulation performance.
  • Passive redesign was the key move: L changed from 1 mH → 12 mH; \(C_o\) changed from 4500 µF → 1500 µF. This cut the ripple far more effectively than forcing the PI to hit crossover targets.
  • Final selection rule: "best measured THD and PF", not exact crossover matching.
Final PI Gains (continuous) Current PI: \(K_p\) = 2.8, \(K_i\) = 17 600  —  Voltage PI: \(K_p\) = 0.055, \(K_i\) = 0.2
Discrete form (\(T_s\) = 20 µs) \(K_{i,i,d}\) = 0.352, \(K_{i,v,d}\) = 4.0 × 10⁻⁶ (\(K_p\) unchanged in both loops)
After PI Controller Waveforms
Stability

Loop-Gain Stability Margins

  • Current loop actual crossover: 14.89 kHz (≈ 3× the 5 kHz target). PM ≈ 86.2°.
  • Voltage loop actual crossover: 5.85 Hz (≈ 2.3× the 2.5 Hz target). PM ≈ 87.6°.
  • Both loops show very large linear stability margins at the selected operating point. However, practical robustness is still limited by duty saturation, sampling effects, and THD measurement-window sensitivity.
  • Higher-than-target bandwidth accepted as a deliberate practical compromise for better harmonic performance.
  • Both loops show very well-damped transient response consistent with phase margins > 86°.
Current loop PM 86.2° Voltage loop PM 87.6° Gain margin ∞ (both loops)
Open-loop margins — current and voltage loop Bode plots
Closed-loop Bode response
Results

Performance — THD & Power Factor

  • Output voltage regulated, settling near 400 V after the startup transient.
  • Input current shaped to follow the line-voltage envelope — sinusoidal and in phase.
  • Measured Power Factor ≈ 0.99 (Simulink value: 0.9999).
  • Representative input-current THD ≈ 4.48% — below the 5% design target.
  • Dual-loop control stable with very large phase margins (> 86°).
Key results (Simulink measurement) Power Factor = 0.9999  —  THD = 0.0448 (4.48%)
Simulink measurement block: PF = 0.9999, THD = 0.0448
Honest Assessment

Limitations — Where the System Falls Short

  • The good THD holds in the chosen steady-state window but can spike up to ~12% in other analysis windows — the system is sensitive to the measurement interval.
  • High current-loop bandwidth (14.89 kHz) is the likely cause of window sensitivity — the fast loop amplifies switching-edge noise depending on where the window lands.
  • The voltage loop is also faster than its target, though still slow enough not to distort the sinusoidal current reference.
  • PIL hardware verification was never closed — no physical TI C2000 (LAUNCHXL-F28379D) board was available. On-target numerics and timing compliance within the 20 µs sample period remain unverified.
  • Summary: Regulation and PF are solid. Harmonic robustness across windows is the weak point. Real-hardware validation (PIL) is future work.
Window-sensitivity note THD can read as high as ~12% depending on the Simulink measurement window position. The reported 4.48% is from the cleanest steady-state window. Future work should widen the analysis to confirm IEC 61000-3-2 compliance across the full line cycle.
Verification Chain

MIL / SIL / PIL Verification

MIL — Model-in-the-Loop Controller runs as a Simulink model inside the closed-loop simulation (Part f/g). THD ≈ 4.92%, PF ≈ 0.99. ✓ Completed.
SIL — Software-in-the-Loop Controller compiled to C code and run on the host computer (Part h). Built on macOS with Xcode Clang (x64). Stronger startup transient observed. ✓ Completed.
PIL — Processor-in-the-Loop Same C code cross-compiled and run on TI C2000 LAUNCHXL-F28379D Delfino. Verifies target numerics, bit-accurate behaviour, and 20 µs timing budget. ⚠ Documented conceptually — hardware not available.
  • MIL vs SIL comparison: Part f (reference sim) THD ≈ 4.48% / PF ≈ 0.99; Part g (MIL) THD ≈ 4.92%; Part h (SIL) execution verified with stronger startup transient.
  • Moving the SIL build to Windows may raise toolchain/path errors; original build used macOS x64 Clang.
MIL — waveform set (Part g)
MIL — THD measurement view
SIL — waveform result (Part h)
Summary

Conclusion

  • Carried the design from spec-based component sizing all the way to model-based verification — a complete MIL/SIL chain.
  • The passive redesign (L: 1 mH → 12 mH, \(C_o\): 4500 µF → 1500 µF) was the key move that brought THD under 5% while keeping PF near 0.99.
  • Dual-loop average current-mode control gave stable, well-damped regulation with phase margins exceeding 86° in both loops.
  • MIL and SIL confirmed the controller survives the move into generated C code with comparable performance.
  • Future work: close the PIL loop on real hardware; investigate and reduce THD window sensitivity (possibly by reducing current-loop bandwidth).
Bibliography

References

  1. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 3rd ed., Springer, 2020.
  2. D. W. Hart, Power Electronics, McGraw-Hill, 2011.
  3. N. Mohan, T. M. Undeland, W. P. Robbins, Power Electronics: Converters, Applications, and Design, 3rd ed., Wiley, 2003.
  4. S. Choudhury, "Average Current Mode Controlled PFC Converter using TMS320LF2407A," TI Application Report SPRA902A, Jul. 2005.